It is known that, when fabricating large scale integrated circuits, in particular when producing the individual wiring planes (e.g., the polysilicon layer or aluminum layer), defects and consequently faults may occur which may cast doubt on the operation of circuits of this type or lead to premature failure.
In order to be able to make a somewhat reliable prediction in this case, test structures in the form of geometric configurations have been developed. It is possible to use the test structures to reliably detect defects within a large area. The bonding pad configurations of customary standard chips are used in order to make contact for test purposes. The test structures are fabricated in small numbers on test chips in parallel with actual production and are then subjected to corresponding test procedures. It has proven to be favorable in this case if the test chips are arranged simultaneously with the actual chips to be produced on the same wafer and thus pass through the same production process.
“Square” test structures in the form of a three dimensional or two dimensional matrix are examples of test structures of this type with the result that it is also possible in principle to detect faults in vertical structures (vias). In particular, testing of the electrical loadability of the vias between the metal planes is particularly important in this case during product or technology qualification. Special acceleration methods can then be used to make a statement on the maximum current-carrying capacity or dielectric strength, while indicating a maximum lifetime and operation temperature.
In order to achieve this, in the case of “downstream” or “upstream” structures, that is to say vias having a corresponding current direction, the respectively critical junction (via to metal track) should be realized with minimal overlap. This is generally the region of the landing pad, that is to say, in the case of real chips, the contact area between two metal planes, on which one or more vias are positioned. The “worst case” can thus be simulated in a test structure, that is to say the worst case is assumed when arranging the contacts and the selected overlap in the test structure for testing.
It is not possible, however, in the test structures, which have been disclosed hitherto, to simulate cases of very high to maximum coverage density. In this case, the problem resides in the fact that process-dictated uncontrolled expansion which results in a distinct projection may occur in the region of the landing pad during fabrication of the uppermost interconnect. The expansion occurs during the exposure and development of the photoresist (resist) and the subsequent patterning of the interconnect and is therefore dictated by the process. Test structures of this type may be used to cover only some of the requisite tests which cannot, however, reliably simulate the critical case at any time but only reflect considerably more relaxed conditions than in product design.